Consulting in Chip Design

In addition to smaller consulting/advice jobs, I consulted for four years (8hrs/week)with Riverstone Networks on high-speed I/O and DDR design, for 3 months (~3hrs/week) for Mediamatics and National Semiconductor on on-chip clocking and I/O design for the one-chip DVD solution, and for two years (8hrs/week) SGI and MIPS for the next generation microprocessors. I was responsible for high speed DDR I/O circuits on Riverstone's 15008 Edge router and I/O's on RS8000 & RS8600.

Bendik's Brief Biography

During my BS-EE at University of Surrey I consulted in electrostatic design related to my thesis work. I then worked one year in a renowned research lab in France in Semiconductor Device characterization and fabrication (SIMOX, SOI devices). After my MS-EE in Devices and VLSI at Stanford University (91) I worked in circuit design, in the area of clocking, power supply, off-chip high speed drivers, sense amplifiers and charge pumps for non-volatile memories. in 1997 I went back to Stanford University to do my Ph. D. in the area of CMOS beyond 10 GHz. In 2000, I joined Matrix Semiconductor and made the idea of 3D memory a reality, by first defining and implementing a new current sensing architecture and taking three generations of silicon through to high volume production. In 2005 I joined Zero G Wireless to invent the building blocks for the fourth generation wireless revolution.

References available on request.