Bendik Kleveland Stanford University (Graduated August 2000) New contact information at: (408) 368-6406 bendikATzerogwirelessDOTcom (Attempt to reduce spam: to e-mail me replace AT with '@' and DOT with '.')

Research:

• Conventional CMOS Interconnects Beyond 10 GHz: Summary.
• My orals summary.pdf and presentation.pdf presented at Stanford November 11, 1999.
• For a copy of my thesis please contact June Wang by e-mail or by phone at 650-725-3706.
• Look at related research in Prof. Simon Wong's group and Prof. Tom Lee's group

Recent Papers:

• High-frequency characterization of on-chip digital interconnects, JSSCC, 2002 .
• Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design, JSSCC, 2001 .
• On-chip inductance modeling of VLSI interconnects, ISSCC, 2000 .
• Monolithic CMOS distributed amplifier and oscillator, ISSCC, 1999 .
• Distributed ESD protection for high speed integrated circuits, IEEE EDL, 2000 .
• Inductance line extraction in a real chip with power grid, IEDM, 1999 .
• 50-GHz transmission lines in conventional CMOS technology, IEEE, MTTS .

Patents:

• 6,515,904 Method and system for increasing programming bandwidth in a non-volatile memory device
• 6,515,537 Integrated circuit current source with switched capacitor feedback
• 6,486,728 Multi-stage charge pump
• 5,969,929 Distributed ESD protection device for high speed integrated circuits (on-line overview).
• 5,898,321 Method and apparatus for slew rate and impedance compensating buffer circuits
• 5,528,168 Power saving terminated bus

Consulting:

• High-speed I/O's, EMI and interconnects - part time consulting.
• Copy of resume.doc for Windows.

Classes:

• Information about a Love and Logic Parent Class.

Vonny's publication:

• Vonny studied baby sleep habits in the bay area.

Personal Highlights